Dynamic RAMs are characterized by having timing parameters that must be respected for proper memory operation. Examples are refresh interval (maximum time between two refresh commands must be issued to the memory), CAS latency (minimum time before the data becomes available after issuing a column address request). There are about several dozens of them described in the memory specification.
These timing parameters are coded in clock cycles assuming a known and constant memory clock frequency and they are typically programmed to the memory controller during the memory initialization. This was sufficient in the old days when the memory frequency was set once during initialization and has never changed since then. For modern battery operated devices power consumption is a critical technical and marketing requirement. A widely used techniques for power saving is dynamic frequency and voltage scaling (DFVS). For aggressive power management DFVS is applied constantly by monitoring the workload applied and adjusting the system performance and power level to match it. Typically DFVS scales CPU and system bus frequencies (sometimes both frequencies must maintain a certain ratio). Often memory controller and the DRAM run on the same clock as the system bus and thus DFVS applied on the system bus clock scales the memory clock as well. Note, that running memory synchronous to the system bus is usually the most power efficient way.
Scaling of the clock frequency used for memory accesses requires updating of the memory controllers timing parameters because they are typically coded in clock cycles. Owing to long latencies in such updating when scaling frequency/voltage, the DFVS algorithm is becoming very conservative since the costs of misprediction are high. Conservative DFVS algorithms therefore are less power efficient because they exploit fewer opportunities for power savings.